This invention relates to a semiconductor device of the type in which an electrode of a capacitor or a plug of each memory cell is formed by chemical vapor deposition, and to a method of manufacturing the semiconductor device.
High integration density of semiconductor devices such as dynamic random access memories (DRAMs) can be achieved when a cell area is reduced. This means that an occupying area of the capacitor of the memory cell decreases inevitably. Nonetheless, predetermined storage capacitance necessary for reading out the memory must be secured to prevent a soft error. In other words, means is necessary for increasing storage capacitance per unit area to attain a high integration density of semiconductor devices. One of such means would be the one that applies an oxide dielectric material having a large specific dielectric constant to a capacitor insulating film. A Ta2O5 film (specific dielectric constant: 20 to 25) has been used at present for the capacitor insulating film in place of a SiO2 film (specific dielectric constant: 3.8) and a Si3N4 film (specific dielectric constant: 7 to 8) that have been used in conventional memories. In memories of a giga-bit scale, however, storage capacitance necessary for readout is not sufficient even when the Ta2O5 film having a large specific dielectric constant is used and capacitors have a three-dimentional structure to increase a substantial capacitor area. Therefore, oxide dielectric materials having a specific dielectric constant of 100 or more, such as strontium titanate: SrTiO3 (STO), Barium Strontium Titanate: (Ba,Sr)TiO3 (BST), lead zirco-titanate: Pb(Zr, Ti)3 (PZT) and SrBi2Ta2O9 (SBT), have been examined for a capacitor dielectric film. PZT and SBT among them can be applied to ferroelectric memories that utilize their ferroelectricity.
To improve electric property (dielectric property), these oxide dielectric materials require film formation and post heat-treatment at a high temperature of at least 400xc2x0 C. to 700xc2x0 C. in an oxidizing atmosphere. In this instance, when a lower electrode is oxidized by oxygen contained in the atmosphere, an insulating film having a lower dielectric constant than that of a capacitor insulating film is formed, inviting the substantial drop of capacitance of the capacitor.
When a barrier layer and plugs positioned below the lower electrode are oxidized, electric conduction is lost between the transistor and the capacitor. Therefore, platinum (Pt) that is relatively stable in a high-temperature oxidizing atmosphere and ruthenium (Ru) and iridium (Ir) that keep conduction even when oxides are formed have been examined as promising materials of the lower electrode. Most preferred among them is Ru as the lower electrode of the oxide dielectric material because it has high fine etching property.
To sum up, storage capacitance necessary for readout might be insufficient in giga-bit scale memory cells even when an oxide dielectric material having a high specific dielectric constant is used because the area the capacitor can occupy is small. To substantially increase the capacitor area, therefore, the capacitor structure must be rendered three-dimentional. For example, process steps are necessary to shape the lower electrode of the capacitor into a three-dimentional structure and then to form the oxide dielectric material of the capacitor, or to shape the lower electrode on the three-dimentional structure that is formed in advance, and then to form the oxide dielectric material.
The article entitled xe2x80x9c(Ba, Sr)TiO3 Capacitor Technology for Gigabit Scaled DRAMsxe2x80x9d in xe2x80x9cTechnical Digest of International Electron Devices and Materials (IEDM)xe2x80x9d, 98, pp. 803-806, describes an example of a three-dimentional structure of a capacitor that uses BST as the material of a dielectric film, shapes electrodes into a convex shape and uses Ru as the material of the electrodes.
The article entitled xe2x80x9cLow Temperature (Ba, Sr)TiO3 Capacitor Process Integration (LTB) Technology for Gigabit Scaled DRAMsxe2x80x9d in xe2x80x9cTechnical Digest of International Electron Devices and Materials (IEDM)xe2x80x9d, 99, pp. 789-792 describes an example of a three-dimentional structure of a capacitor that uses BST as a material of a dielectric film, shapes electrodes into a concave shape and uses SrRuO3 as the material of the. electrodes.
Furthermore, the article entitled xe2x80x9cDevelopment of Ru/Ta2O5/Ru Capacitor Technology for Gigabit Scale DRAMsxe2x80x9d in xe2x80x9cTechnical Digest of International Electron Devices and Materials (IEDM)xe2x80x9d, 99. pp. 793-796 teaches to sputter and etch away unnecessary Ru in a formation step of a lower electrode of a capacitor made of Ru.
However, none of the references cited above recognize the following problems. In other words, these references do not teach or suggest at all the technical features of the present invention that will be explained below in detail.
Studies conducted by the inventors of the present invention have revealed that the following problems develop when a capacitor having a three-dimentional structure is fabricated by using the prior art technologies described above.
The three-dimentional structure of the lower electrode fabricated and examined by way of experiment by the present inventors will be explained with reference to FIGS. 1a to 1c. All the drawings depict the section. First, a Ru lower electrode film 5xe2x80x2 having a film thickness of 400 nm is deposited on plugs 1 made of Ru and a plug interlayer insulating film 2 made of SiO2, for example (FIG. 1a). The lower ruthenium electrode film 5xe2x80x2 is then etched into a cylinder shape, an elliptic cylinder shape or a rectangular shape to the surface of the plug interlayer insulating film 2 by known photolithography and dry etching, giving lower electrodes 5 having a three-dimentional structure (FIG. 1b). In a giga-bit scale semiconductor device having a minimum feature size of not greater than 0.15 xcexcm, however, it is difficult to vertically etch the ruthenium electrode having the shape described above. Therefore, the etching shape becomes such that bottom portion becomes wider than the top portion as shown in FIG. 1b. After the lower ruthenium electrode 5 is etched, an oxide dielectric material 6 made of BST, for example, is deposited by chemical vapor deposition (CVD). An upper electrode 7 made of Ru, for example, is then deposited by CVD, completing the capacitor (FIG. 1c). In this case, since the bottom portion of the lower electrode has a wide patterning shape as described above, the adjacent capacitors are so close to each other that electric interaction occurs between them. When a sufficient gap is secured between the bottom portions of the electrodes, a sufficient area of the top surface cannot be secured, on the contrary, and the sectional shape of the electrode becomes triangular with the result that the surface area of the three-dimentional electrode decreases.
Another structural example of a three-dimentional structure fabricated and examined by the present inventors by way of experiment, in which holes are formed into a silicon oxide film, fine patterning of which is easy, from the film surface, and a Ru lower electrode is then deposited by CVD, will be explained with reference to FIGS. 2a to 2c. All the drawings show the section. First, a 400 nm-thick capacitor interlayer insulating film 3 made of SiO2, for example, is deposited by CVD on plugs 1 made of Ru and a plug interlayer insulating film 2 made of SiO2, for example. Holes reaching the surface of the plug interlayer insulating film 2 are then formed in the capacitor interlayer insulating film 3 into a cylinder shape, an elliptic cylinder shape or a rectangular shape, by known photolithography and dry etching. Lower ruthenium electrodes 5xe2x80x2 having a film thickness of 30 nm are thereafter deposited by CVD, giving the lower electrodes having the three-dimentional structure (FIG. 2a). However, it is necessary in this case to remove the portion of the lower electrode 5xe2x80x2 deposited on the top surface of the capacitor interlayer insulating film 3 and to electrically isolate adjacent capacitors from one another. According to a physical sputter-etching process that is generally employed to remove the film in self-alignment, the electrodes deposited on the top surface of the interlayer insulating film can be removed preferentially, but the portion to be utilized as the lower electrode is simultaneously exposed to the etching atmosphere. In consequence, the film thickness decreases on the side wall portion of the cylinder near the top surface and on the bottom portion near the center, and the lower electrode 5 has concretely the shape as shown in FIG. 1b. The oxide dielectric material 6 made of BST, for example, is then deposited by CVD and the upper electrode 7 made of Ru, for example, is likewise deposited by CVD, completing the capacitor portion (FIG. 1c).
This process invites the problems that the capacitor area decreases due to the drop of the height of the sidewall portion and the capacitor resistance increases due to the decrease of the film thickness of the lower electrode. Therefore, a method of electrically isolating the adjacent capacitors is preferred that does not include the step of sputtering and etching away a part of the lower electrode.
According to one aspect of the present invention, a first electrode of a capacitor electrically connected to one of a pair of active regions of a transistor in each memory cell is formed by the steps of forming a deposition preventing film on an insulating film in such a manner as to define a desired pattern of the first electrode of the capacitor and forming a film of a first conductive material to the pattern defined by the deposition preventing film. Next, a dielectric film is formed at a predetermined temperature on the film of the first conductive material and on the deposition preventing film, or on the film of the first conductive material and on the insulating film by removing the deposition preventing film. At this time, the material of the first conductive material is Ru, Pt or Ir that does not lose conduction even when exposed to the predetermined temperature for forming the dielectric film. Next, a second conductor layer that serves as a second electrode of the capacitor is formed on the dielectric film.
According to another aspect of the present invention, a first electrode of a capacitor electrically connected to one of a pair of active regions of a transistor in each memory cell is formed by the steps of forming a seed film on an inner surface and a bottom surface of holes formed in an insulating film, or further on the insulating film, whenever necessary, in accordance with a desired pattern of the first electrode of the capacitor, and forming a film of a first conductive material into the desired pattern by utilizing the seed film. Next, a dielectric film is formed at a predetermined temperature on the film of the first conductive material and on the insulating film. At this time, the material of the first conductive film is Ru, Pt or Ir that does not lose conduction even when exposed to the predetermined temperature for forming the dielectric film. A second conductor layer serving as a second electrode of the capacitor is formed on the dielectric film.
According to still another aspect of the present invention, holes are formed in an interlayer insulating film in a semiconductor device including a plurality of memory cells, and a lower electrode is selectively deposited on a side surface or an inner surface and a bottom surface of each hole when the lower electrode of a capacitor of each memory cell is deposited by chemical vapor deposition (CVD) on an inner side wall of each hole. Since the lower electrodes between adjacent capacitors are not electrically connected in this case, a process step of physically sputtering and etching away the electrode deposited on the top surface of an interlayer insulating film, that has been necessary in the prior art technologies, can be omitted, and the problem of undesired etching of the portion necessary as the lower electrode during this step can be solved, too. In addition, even when the lower electrode material such as Ru is deposited to the top surface of the interlayer insulating film, the step of removing the film on the top surface of the insulating film can be simplified and the process time can be shortened provided that the film thickness of the lower electrode material on the interlayer insulating film can be made sufficiently smaller by selective growth to the inner surface of the holes than the thickness of the film formed by the lower electrode material deposited to the inner surface of the holes. Incidentally, the material of the dielectric film of the capacitor is not limited to oxides, and dielectric materials made of nitrides may be used, too.